The F21c has a parallel I/O port on the chip located at the top of the die. Their are a total of 15 i/o bits on the port. The bottom 8 bits P0-P7 are general purpose i/o bits. Their direction is controled by bits 0-7 in the port direction control register. Bits 14 and 15 also control whether P0 and P1 are pulled up or pulled down. P0 has only 1/2 and P1 has only 1/3 of the drive of bits P2-P7 on this prototype. This restriction is there for transistor characterization tests.
Bits P8-P13 may also serve other functions. If used for input bit P8 is the Serial Network input line Ni, and although it can be read as a parallel port bit it will also act as serial network input. P9 is both a parallel i/o bit or the Serial Network output, No. If P9 is set to input then the Serial Network output is tri-stated. This allows multple F21 No to be connected to one F21 Ni. P10-P13 if set to output will provide SRAM address lines A10-A13.
Port Bit P13 also has an experimental echo timing function. An echo timing unit can be used with the Port bit P19 if read will provide the state of the Ci Clock input line used with count down registers to provide the timing for the Analog, Video, and Network coprocessors.
F21c will offer a will offer an echo timing circuit that will measure the time that is needed for a pulse to return from a line to an accuracy of about 100ps. (.1ns) Being able to measure a pulse reflect to a fraction of a nanosecond could be a useful feature for some specialized hardware as it could measure distance to about an inch in signals traveling at the speed of light. Perhaps people will want to experiment with lasers or radar interfaces. Chuck has suggested various uses including using it as a single bit parallel keyboard interface. If there was an inch of wire separating the keys connected parallel to ground this unit could determine which key was pressed by timing differences. Longer timing measurements will also involve use of the on chip Real Time Clock