Updated 6/3/97
The F21 chip die is about 4x3 mm although much of the space on this die is unused. Their are 68 pads on the die and 68 pins on the chip on the plcc package. The PGA package with 64 pins required the 2x4mm die size. The working die size is about 2mm square. In this size the silicon may be manufactured for only a few cents in large quantity. The cost of packaging with 68 pins will be greater than the cost of the die in large quantity. Other packages for F21 may also be offered.
The F21 chips has 68 pads located around the outsid of the die. These pads are assigned as follows:
F21c Packaging
C+ Core Power (2)
C- Core Ground (2)
P+ Pads Power (3)
P- Pads Ground (3)
A+ Analog Power
A- Analog Ground
P0-P7 Parallel port i/o
WE Write Enable
SRAM Select SRAM
ROM Select ROM
RAS Row Address Strobe for DRAM
CAS Column Address Strobe for DRAM
D0-D9 10 lower data bits
AD10-AD19 10 upper data bits/multiplexed upper address bits for DRAM/ROM
A0-A9 10 lower address bits
A10-A13 (P8-P10) 4 upper address bits for SRAM/parallel port i/o
Ni (P11) Network input/parallel port i/o
No (P12) Network output/parallel port i/o
Ci (P19) Xtal/oscilator clock input/parallel port in bit 19
R RGB video Red
G RGB video Green and sync
B RGB vide Blue
Ao Analog Output
Ai Analog Input
Reset Chip reset line
F21c die pads
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
A12/P10 A11/P9 A10/P8 P7 P6 C+ C- P5 P4 P3 P2 P1 P0 RAM ROM RAS
9 Reset CAS 60
10 Ni/P11 P+ 59
11 No/P12 P- 58
12 A13/P13 WE 57
13 Ao A9 56
14 Ai A8 55
15 Ci A7 54
16 B A6 53
17 A+ F21c Pads A5 52
18 R A4 51
19 G A3 50
20 A- A2 49
21 AD19 A1 48
22 AD18 A0 47
23 AD17 D0 46
24 AD16 D1 45
25 AD15 D2 44
26 AD14 D3 43
AD13 AD12 AD11 AD10 P+ C+ C- P- D9 D8 D7 D6 P+ P- D5 D4
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
PIN-OUT same as die
F21c Prototypes 68-Pin Ceramic LCC:
Production F21 68-Pin PLCC: