F21 Serial/Network Coprocessor
Network Topology and Robotics Example

The F21 microprocessor contains a Serial/Network Coprocessor to facilitate the construction of a network of computers, or a multiprocessing computer. The Serial/Network Coprocessor scans the serial bit stream for instructions and node addresses and provides DMA and CPU interrupt capability in hardware.

Following are some explanations of possible network topologies, methods of pre and post processing of network data, variations in network topologies, and some robotics examples. 

                      Simple F21 Network Topologies

1. Ring.          +-> F21 > F21 >-+
                  |               |
                  +-< F21 < F21 <-+
The F21 provides all the hardware you need to run a ring. The ring can operate in one of two modes, sequential or pipelined. In the sequential mode one or more processors are allowed to transmit at one time. In the pipelined mode half of the processors transmit at one time, but none of them may echo data. 
2. Star.
                 +-> F21 >--+
                 |          |
       +-> F21 >-+-> F21 >--+-->-+
       |         |          |    |
       |         +-> F21 >--+    |
       +-------------------------+
The star mode might require amplifying the output of one F21, but will not require ORing the outputs of the nodes back to the hub processor input since the output of the F21 serial/network coprocessor is tri-stated and will float when not sending output to the network. In this star only one F21 can echo, so only one can have the echo bit turned on at a time. This topology can not operate in the pipeline mode, but it does permit more complex topologies to be constructed.

The star is possible because there is an echo bit in the network configuration register.

When echo is turned on data is echoed with a 1 bit delay if there is no DMA. If the SOM header matches, then there is DMA to memory, and then there is more than one bit delay, but if the echo bit is on it will still echo.

CPU Pre and Post Processing of Serial/Network Data

The code I wrote for preprocessing does 2 things, first it checks for any sequence of five or more 0 or 1 bits a row. (the actual number may greater than 5, but 5 is the number in fiberchannel) The second step is to check each data word against any assigned SOM (or SOM group match). If the data has too many consecutive 0 or 1 bits, or is a match to a SOM then it must be altered. This is done by first simply xoring it with AAAAA to see if that makes it legal. Then when it is transmitted, at the end of the the message the address and xor pattern of all corrected words must be added to the message.

On the post processing all of these xored words must be corrected before the message is finished. A length, and a checksum, and maybe some other stuff will be added to message packets also.

Since a DMA is always followed by an interrupt of the CPU, the CPU will go to an interrupt routine. It will determine from the configuration register that the source of interrupt was the network. Then it will post process the message, and place the DMA transfer into the real destination address rather than just to the communication buffer where it is normally sent.

For simple remote interrupts, a short message can include the address for the real interrupt (and checksum and maybe message number and length or whatever extra stuff we add also). Then after processing the data in the normal manner from the interrupt vector to post process a message transfer, it would then jump to the vector address in the remote execute type transfer.

The Serial/Network Coprocessor is designed to be internally compatible with operation at fiberchannel speeds of up to a gigahertz. In fiberchannel an 8 bit byte is changed into a 10 bit number with a table lookup to get the safe data with no more than 4 consective 0 or 1 bits. We can not do it this way with 20 bit numbers. We can not use a 20 bit table, or expand from 20 to 25 since the hardware sends 20 bit patterns.

Normally in a ring all processors will have the echo bit set except the master processor. The master processor will not normally echo, but will be able to capture and retransmit messages that must go past the master to get to an address upstream of that of the sender.

Some variations in F21 network topologies. 

1. Ring   +-> F21 > F21 >-+          * Advantage: ring or pipeline mode,
          |               |                       most general
          +-< F21 < F21 <-+

2. Star     +-> F21 >--+             * Only one processor at an ORed gate
            |          |               will echo or transmit at one time
  +-> F21 >-+-> F21 >--+-->-+
  |         |          |    |
  |         +-> F21 >--+    |
  +-------------------------+

3. Bridged rings   +-> F21 > F21 >-+
                   |               |
                   +-< F21 < F21 <-+
                              ||      Parallel Port as software bridge
                   +-> F21 > F21 >-+
                   |               |
                   +-< F21 < F21 <-+

4. Multiring (semi grid)

            +-> F21 > F21 > F21 > F21 >--+   * some piplelined operation
            |    ||    ||    ||    ||    |
  +-> F21 >-+-> F21 > F21 > F21 > F21 >--+-->-+  || parallel port
  |         |    ||    ||    ||    ||    |    |
  |         +-> F21 > F21 > F21 > F21 >--+    |
  +-------------------------------------------+

5. Can of Worms *                  +-> F21 > F21 >--+
                                   |                |
            +-> F21 >-+            +-> F21 > F21 >--+--> F21 > F21 >-+
            |         |            |                |                |
            +-< F21 <-+            +-> F21 > F21 >--+      +-< F21 <-+
                 ||                |                       |
            +-> F21 > F21 > F21 >--+                       |
            |                                              |
  +-> F21 >-+-> F21 > F21 > F21 > F21 > F21 > F21 --+-->-+ |
  |         |                                       |    | |
  |         +-> F21 > F21 > F21 > F21 > F21 > F21 --+    | |
  |                                                      | |
  +-< F21 <---------------------------------------------< or
       ||
+---> F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 >-+
|      ||    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||   |
| +-< F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 <-+
| |    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||
| +-> F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 >-+
|      ||    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||   |
+---< F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 <-+

 * any combination of, ring, star, bridged rings, and multirings.

Robotic Examples 




                   Simple F21 Robot Based on One F21



 camera ->     image recognition   image output  -> TV and RGB Monitor
  sound -> F21 speech recognition  speech output -> speaker
sensors ->     reflexes  planning  coordination  -> motors





            Anthropomorphic Robot Network Topology Example



This topology presents an example where a few F21 provide a standard
subsumption architecture reflexive base, some F21 are used for dedicated
I/O, and some F21 are used for specialized or generalized nervous system
functions.  The number of dedicated or general purpose processors can
be varied freely.  Software contains a combination of simulated
neural network reflexive behaviour, conventional expert systems that can
explain their reasoning, and agents that arbitrate the competing neural
nets and expert systems.  It is implemented on top of a network and OS
system layer and underlying F21 hardware.  The details of this particular
Anthropomorphic Robot Topology are somewhat arbitrary and is meant as an
example only.


                        +--------< F21 <-----------------------------------+
                        |                                                  |
                        +------------------------------+                   |
      Video Camera >--> F21          Video Camera >--> F21                 |
             Sound >--+ |                   Sound >--+ |                   |
                        |                              |                   |
      +---+---+---+---+-+-+---+---+      +---+---+---+-+-+---+---+---+     |
     F21 F21 F21 F21 F21 F21 F21 F21    F21 F21 F21 F21 F21 F21 F21 F21    |
      retinal - auditory neurons         retinal - auditory neurons        |
     F21 F21 F21 F21 F21 F21 F21 F21    F21 F21 F21 F21 F21 F21 F21 F21    |
      instantaneous and temporal              pattern recognizers          |
     F21 F21 F21 F21 F21 F21 F21 F21    F21 F21 F21 F21 F21 F21 F21 F21    |
      +---+---+---+-+-+---+---+---+      +---+---+---++--+---+---+---+     |
                    |                                 |                    |
                    +-----------------+---------------+                    |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+    |
     F21 F21 F21 F21 F21 F21 F21 F21     F21 F21 F21 F21 F21 F21 F21 F21   |
     3D imaging - object definition      speaker - sound identification    |
     F21 F21 F21 F21 F21 F21 F21 F21     F21 F21 F21 F21 F21 F21 F21 F21   |
              visual cortex                     audio memory               |
     F21 F21 F21 F21 F21 F21 F21 F21     F21 F21 F21 F21 F21 F21 F21 F21   |
      +---+---+---+---+---+---+---+      +---+---+---++--+---+---+---+     |
                    |                                 |                    |
                    +-----------------+---------------+                    |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+    |
     F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21   |
     F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21   |
     F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21 F21   |
      +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+    |
      memory        perception        |       integration     language     |
                                      +---------------------------------+  |
  +-< F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 <-+  |
  |    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||      |
  +-> F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 >-+  |
       ||    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||   |  |
  +-< F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 < F21 <-+  |
  |   rationalization and logic     expert agents     management agents    |
  |                                                                        |
  |                                                                        |
  |      Subsumption Architecture Autonomic Nervous System in Body         |
  |        sensation            reflexes        motor control              |
  +-> F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 > F21 >----+
       ||    ||    ||    ||    ||    ||    ||    ||    ||    ||    ||
            sensors                                outputs




Return to F21 network document