F21 Memory Specifications

The memory interface processor provides memory access to all processors giving lowest priority to the CPU. The I/O coprocessors can be turned on or off by the CPU, and can run continuously executing their own instructions, or can interrupt the CPU to process their data buffers or instructions.

MEMORY

CONFIGURATION
 Typical: 0-5 DRAMs, 0-3 SRAMs, 1 ROM

    5 1Mx4 Page-mode DRAMs: Toshiba TC514400APL-80
 or 1 1Mx16 and 1 1Mx4    :
 and/or 3 8Kx8 SRAMs      :

    1 8-bit PCMCIA card   :
 or 1 8-bit ROM           :

CONFIGURATION REGISTER (C)

A number of options are specified in the Configuration Register (C). For example, timing is determined by internal delays. These may be adjusted to suit.
    bit 20 .... .... .... .... ...0
pattern: - pp-s -r-- -3tt 5f-- -iii
           xx-0 -0-- -000 01-- -iii
ROM page 0, slow RAM, slow ROM, 5+, -40%, 1Mx4DRAM, normal refresh

 pp - ROM page (D19,18)
 tt - timing (dependent upon voltage, temperature, process)
      00  40% slow
      01  20% slow
      10  nominal
      11  20% fast
  3 - Power (timing dependent upon voltage)
      0  5.0 V
      1  3.0 (55% fast)
  r - ROM timing
      0  250 ns
      1  150
  s - RAM timing
      0  25 ns
      1  12
  5 - 512-word page (for 256Kx4 DRAMs)
         A8 is multiplexed differently for a RAS address:
         A9  8  7  6  5  4  3  2  1  0
      0  A19 18 17 16 15 14 13 12 11 10
      1  A19  9 17 16 15 14 13 12 11 10
  f - CAS before RAS refresh on DRAM access
      0  Refresh (For some DRAMs, the first 8 accesses after power-up
                  must be refresh.  RAS address must change on each.)
      1  Normal (To be set during boot)
iii - Interrupts
      1--  Video
      -1-  Network
      --1  Analog

The following patterns are commonly used:
    Power-up  C0000
  5V 1M DRAM  D0200 12ns SRAM
5V 256K DRAM  C0280
  3V 1M DRAM  C0600
C may be read, changed and rewritten.

TIMING

A memory access has 10 ns overhead in addition to the access time. On a write to memory, data is latched on the rising edge of WE for RAM, ROM and IO devices controlled by these signals; but on the falling edge for DRAM. RAM and ROM are not clocked, but CAS is. WE is the signal to measure to verify timing.

The next instruction fetch begins as soon as no memory instructions (# @ ! jump) are pending.

ADDRESS MAP 6/1/97 DATA
address         pattern
000000 - 0FFFFF        DRAM 20 bit        1 M words (or 256K words)
180000 - 1BFFFF        slow 8 bit ROM     1 M bytes as 4 256k pages
1C0000 - 1FFFFF        fast 8 bit ROM     1 M bytes as 4 256k pages
100000 - 103FFF        slow 20 bit SRAM   16 K words
140000 - 143FFF        fast 20 bit SRAM   16 K words

not yet updated for F21c
address         pattern
16BAAA P        1C1000 I/O port data register
16BAAA Pd       1C1000 I/O port direction register
168AAA Ca       1C2000 analog Configuration register
148AAA EOM      1E2000 End Of Message pattern register
14EAAA SOM      1E4000 Start Of Message pattern register
142AAA Cn       1E8000 network Configuration register
142AAA Cv       1E8000 video Configuration register
14AAAA Cm       1E0000 main Configuration register
POWER-UP ADDRESSES
 CPU     Audio   Video   Serial
 1AAAAA  0xxxxx  0AAAAA  0xxxxx
 page 3  off     off     off
CPU boot address 1AAAAA in slow 8 bit ROM is pattern 00000 on the pins

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